1. Field of the Disclosure
This disclosure relates generally to computer systems, and more specifically to systems and methods for enabling one or more processor cores to run at a higher speed than other processor cores.
2. Description of the Related Art
Many modern processors incorporate multiple processing cores per physical package. Typically, each of these cores exposes one or more logical processors to software. Each core typically includes register state for each of those logical processors, one or more caches, and one or more execution pipelines. Each physical package has thermal and power limits that prevent all cores within that package from running simultaneously at full speed for prolonged periods. Therefore, when all cores are simultaneously active, the package's power control unit (PCU) forces those cores to run at a “baseline” speed. This baseline speed is typically the advertised speed for the processor.
In some of these multi-core processors, if only one (or a small number) of cores is active on a given package, that package's PCU can run that core (or cores) at a speed that is higher than the baseline speed without violating the thermal and power constraints of the package. In one example, this higher speed is 1.1 to 1.5 times faster than the baseline speed, yielding a faster clock rate and faster processing speed for threads running on that core. This facility is referred to herein as “turbo mode”. The number of processors that need to be inactive (or quiesced) for the remaining processor(s) to reach turbo mode is referred to herein as the “turbo quorum”. The current trend, which is expected to continue, is for the ratio between turbo mode speeds and baseline speeds to increase over time as new generations of processors are delivered.
Other multi-core processors include an asymmetric performance environment in which a fixed set of processors in a system is configured to run faster than the others. In such an environment, threads running contended critical sections could be scheduled or dispatched onto the faster processors to improve overall performance of a group of coopering threads.